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Rust SIMD compiles to GPU warps now — same code, two processors

August 14, 2026 · the bunny lab

The receipts

VectorWare published "Rust SIMD on the GPU" (vectorware.com, reported 2026-08-10 via the Rust feeds), demonstrating Rust's portable SIMD — the unstable core::simd module behind #![feature(portable_simd)] — compiling to GPU warp instructions. The same vectorized Rust code runs on CPU vector units and on the GPU, unmodified.

Separately, This Week in Rust 664 (2026-08-12) carried a dense week for the toolchain: the compiler moved to LLVM 23, fs_set_times and c_variadic_naked_functions stabilized, and Cargo approved the hints.min-opt-level RFC. Details below, each with its own caveats.

Our read: the SIMD story is the one worth your weekend. CPU vector code and GPU kernels have been two codebases with a foreign-function bridge between them for as long as both have existed. This is the first credible sketch of them being one codebase — sketch, not shipping product.

The mechanism: a warp is a vector unit

The core observation is that a GPU warp is a vector unit whose lanes are individually addressable. Simd<T, 32> maps almost one-to-one onto 32-lane warp hardware, which makes the translation table short:

Working today per the post: elementwise ops, reductions, shuffles, masks, select operations, and horizontal reductions. Planned, not shipped: composing threads + SIMD + async, lowering matrix-shaped SIMD to tensor cores, and auto-vectorizing scalar loops.

The fine print (read before you architect around it)

Three constraints, all stated in the source, all load-bearing:

  1. Nightly-only. portable_simd is still an unstable feature; as of early 2026 std::simd has no stabilization date. Anything you build rides nightly.
  2. NVIDIA-only. The current backend targets NVIDIA hardware exclusively.
  3. Zero-cost only at warp width. The mapping is free when your vector width matches the warp's lane count. Arbitrary permutations may need multiple instructions or shared memory, and horizontal operations act as synchronization points that constrain the scheduler.

Our read: this is a crack in the CPU/GPU wall, not a doorway. The right move this week is to read the post and measure how much of your CPU/GPU split it would erase — not to erase it yet.

Also this week (TWiR 664, 2026-08-12)

What to do about it

Sources

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